This invention relates to the field of metal or alloy electrochemical deposition (ECD) for filling narrow and high aspect ratio openings. In particular, the invention discloses new methods which enhance reliable, fast, and void-free filling of very small openings, with large aspect ratios, such as vias and trenches in semiconductor devices, thin film heads, electronic high density packages, or micro electromechanical system (MEMS) devices. The new methods are particularly effective for the so called “Damascene” and “Dual Damascene” copper interconnects, providing fast, reliable, and void-free copper filling by electroplating inside vias and trenches in the manufacture of semiconductor devices.
There are two methods to fill patterned openings by electroplating (“electrofilling”). In one method, an insulating mask such as an oxide, photoresist, or polyimide layer is patterned over a conductive metallic surface (or a “seed layer” or “plating base”), exposing the metallic surface only at the bottom of the openings. Electroplating is carried out through the openings in the insulating mask, and is confined inside the openings of the mask. Usually, following the plating, the insulating mask is removed and the seed layer (which was covered by the insulating mask) is etched away. This method is often used in the fabrication of, for example, coils and other metallic structures of thin film heads, metallic conductors in high density packages, and in MEMS devices.
In the other method, sometimes referred to as “Damascene” or “Dual Damascene”, an insulating (or dielectric) layer is first pattern-etched to form openings in it. Next, at least one metallic layer is deposited over the insulating layer to metallize its top surface (field), as well as the sidewalls and bottom surfaces of the openings. The metallic layer(s) serves as a conductive plating base (or “seed-layer”), to provide low resistive electric path for the electroplating current. Electroplating is then carried out over the entire metallized surface, including the field and inside the patterned openings. Following plating, the plated metal and any metallization (adhesion, barrier, or seed) layers above the field, as well as any excess plated metal over the openings, are removed by etching, polishing, or by chemical mechanical polishing (CMP). This results in metallic filled vias or trenches (or grooves), surrounded by a dielectric. This method is used, for example, to produce metallic interconnects in semiconductor integrated circuits devices.
Usually, when using electrolytes without surface active additives, the plating rate inside the openings is slower than at the field. Due to higher electric field at the top corners of the openings, the local current density (and plating rate) is higher at the top corners, leading to faster growth and pinching-off of the top corners. This leads to deleterious voids in the filling, as shown in FIG. 1. Also, during electroplating, the relatively stagnant electrolyte inside the openings results in poor replenishment and depletion of the plating ion there. This leads to slower plating rate inside the openings than over the field, resulting in voids in the filling (cf. FIG. 1). The plating ion depletion is more severe at the bottom of the openings, and less severe near the top corners. The plating ion concentration gradient produces increasing concentration polarization, which leads to a decreasing plating rate along the depth of the opening. These inherent void-forming problems become more severe with decreasing width and increasing aspect ratio of the openings. The higher the aspect ratio (AR) of the opening, the slower the plating rate inside it, relative to the field. These problems result in poor or incomplete (voids) filling of high AR openings (cf. FIG. 1).
Aspect ratio (AR) is defined herein (cf. FIG. 1) as the ratio between height (or depth), h, of an opening and its smallest lateral dimension, W (width of a trench, or diameter of a via):AR=h/W The openings may consist of, for example, vias or trenches (or grooves) in a dielectric layer, such as used in the fabrication of interconnects in semiconductor integrated circuit devices.
The filling problems become more severe with decreasing lateral dimension W and increasing AR of the openings. For example, in today's most advanced copper filling of trenches and vias in integrated circuit interconnects, the openings may have an aspect ratio as high as 8:1 (h=1.4 μm; W=0.18 μm), and future trench and via openings will likely require W≦0.10-0.13 μm, and AR≧10:1. Reliable, void-free filling of such narrow and high AR openings imposes a great deal of difficulty.
In order to overcome the natural tendency to form voids, commercial electrolytes, such as acidic copper sulfate, usually include proprietary surface active “brightener” and/or “leveler” additives. The proprietary additives usually comprise organic compounds with functional groups containing sulfur and/or nitrogen atoms. These compounds adsorb onto growth sites of the depositing metal surface, thereby inhibiting (or suppressing) the metal deposition rate. The adsorption and its associated inhibition lead to smaller (finer) grains of the depositing metal, thus producing smoother and brighter deposits. Leveling is obtained by higher concentration of inhibitor (or additives) at protrusion tips sticking into the diffusion layer, thereby inhibiting (or suppressing) their growth. As a result, inhibition is stronger at protrusions, compared with the flat surface. In much the same way, the relatively stagnant electrolyte inside narrow openings results in poor replenishment and depletion of the inhibitor there. This depletion results in reduced inhibition and faster growth inside the openings. Due to better supply of the inhibitor at the top corners and the field, inhibition is stronger at the top corners of openings and at the field (compared with inside the openings). The reduced inhibition inside narrow openings speeds up the plating rate there (relative to the field), thus facilitating void-free filling (or “superfilling”) of narrow openings with large aspect ratios. The mechanism of superfilling narrow openings, using inhibiting additives, was proposed in several publications. For examples, see an article entitled: “Damascene copper electroplating for chip interconnects”, by P. C. Andricacos, at al. in IBM Journal of Research and Development, Vol. 42(5), pp. 567-574, 1998, and an article entitled: “Copper On-Chip Interconnections”, by P. C. Andricacos in The Electrochemical Society Interface, pp. 32-37, Spring 1999.
Clearly, in order to achieve void-free “superfilling” of narrow openings, the beneficial effect of inhibition gradients must overcome the intrinsic void-forming effects due to (a) higher electric field (and current density) at the top corners and, (b) decreasing plating rate inside openings along their depth due to depletion of the plating ion there.
As openings get narrower, and the aspect ratio increases, void-free ECD-filling becomes harder and harder to control. While wider openings may fill well, narrower ones may have voids, and vice versa. For example, see an article entitled: “Factors Influencing Damascene Feature Fill Using Copper PVD and Electroplating”, by J. Reid et al. in Journal of Solid State Technology, Vol. 43(7), pp. 86-103, July 2000. Process latitude, such as the useful range of additive concentration and/or plating rate, becomes very tight and hard to control.
Prior art ECD tools and methods commonly employ relatively slow laminar (or “natural”) flow of electrolyte across the substrate's surface. For example, U. S. Pat. Nos. 6,080,291, 6,179,983, and 6,228,232 employ a perforated (or “diffusion”) plate or a porous membrane, placed between the anode and cathode (substrate), in order to achieve laminar flow across the substrate's surface. Such flow results in a relatively thick diffusion layer. The thick diffusion layer limits the useful plating rate to only about 0.3-0.4 μm/min, thereby limiting the throughput of single-wafer plating modules. In addition, prior art Cu-plated wafers usually display relatively rough, matte or semi-matte, surfaces. The rough plated surfaces include protrusions or bumps over filled openings, as well as spikes (or “balloons”) and steps (or “humps”) at boundaries between the field and patterned arrays of narrow openings (cf. FIG. 5). Such spikes, humps, or bumps cause excessive erosion and dishing during successive CMP steps and must be eliminated or minimized. Other prior art ECD tools, such as the one disclosed in U.S. Pat. No. 6,176,992 by Talieh, employ brush plating. The brush rubs the substrate's surface during plating. This is claimed to result in more planar plating after filling the openings. However, the continuous rubbing generates particulates due to wear of the brush or pads, or from the depositing metal.
Also, prior art ECD tools and methods often rely on wafer rotation to improve axial uniformity. However, unless certain strict conditions (such as no edge effects, infinite wafer's radius, infinite electrolyte volume, low plating ion concentration, and laminar flow) are satisfied, the wafer rotation creates non-uniform electrolyte flow across its surface. While electrolyte flow is slow at the center of the wafer, its (tangential) velocity increases with the radius. That velocity difference increases with rotation speed. As a result, the thickness of the diffusion layer varies as a function of the radius R (cf. 22 in FIG. 2). It has a maximum at the center of the wafer and gradually decreases along the radius, toward the edge of the wafer. The non-uniform diffusion layer produces severe non-uniformity of the plated layer along the radius of the wafer. It may also lead to deleterious voids in ECD-filled openings (such as trenches or vias) at certain radii of the wafers. These problems become more severe with increasing rotation speed and wafer diameter.